{"id":"1986881e-c855-4806-a347-9fffbec633f4","company":{"id":"1b1bcdf6-9958-11f0-addb-0a892d3d843c","company_stack":[],"company_gallery":[],"company_stats":[],"company_about_section":null,"company_benefit_section":[],"company_testimonial_section":[],"company_culture_section":[],"onboarding_process":null,"ticker_logos":[],"gtn_companies":[],"role_category":[],"cta_color":"#333333","name":"NXP Semiconductors","short_name":"NXP","slug":"nxp","description":"NXP Semiconductors N.V. is a Dutch semiconductor manufacturing and design company with headquarters in Eindhoven, Netherlands. It is the third largest European semiconductor company by market capitalization as of 2024.","short_description":"<p>NXP Semiconductors N.V. is a Dutch semiconductor manufacturing and design company with headquarters in Eindhoven, Netherlands. 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The role focuses on enabling verification teams with robust regression systems, automation frameworks, and advanced methodologies (UVM, coverage, Continuous Integration flows) to improve productivity, debug efficiency, and time-to-tapeout.<br/><br/><h3> Digital Verification CAD Support &amp; Methodology Enablement</h3><br/><ul> <br/> <li>  Act as the primary support interface for Design &amp; Verification (DV) teams to troubleshoot issues in simulation, regression, coverage, and debug flows </li> <br/> <li>  Collaborate with DV teams to identify bottlenecks and provide practical solutions or workarounds </li> <br/> <li>  Support adoption of modern verification techniques (coverage-driven, formal, emulation) through guidance and issue resolution </li> <br/> <li>  Deploy, integrate, and maintain CAD tools, scripts, and environments supporting digital verification flows </li> <br/> <li>  Provide day-to-day support for EDA tools (VCS, Xcelium, Verdi, vManager, etc.) and resolve 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Required Qualifications</h3><br/><ul> <br/> <li>  Bachelor's / master's degree in Electronics Engineering </li> <br/> <li>  8–12 years of experience in Digital Verification / CAD / Engineering Support-related roles </li> <br/> <li>  Strong understanding of digital verification flow (simulation, regression, coverage, debug) </li> <br/> <li>  Hands-on experience with System Verilog and UVM (for debugging/support perspective) </li> <br/> <li>  Proficiency in scripting/programming (Python, Tcl, Perl, or similar) </li> <br/> <li>  Experience in Linux-based environments </li> <br/> <li>  Experience with EDA tools (VCS, Xcelium, Verdi, vManager, etc.) </li> <br/> <li>  Exposure to regression environments, CI/CD systems, and compute farm usage </li> <br/> <li>  Familiarity with AI/ML-based DV tools (e.g., Cadence Verisium AI) is a plus </li> <br/> <li>  Basic understanding of SoC/ASIC architecture and RTL design concepts </li> <br/></ul><br/><br/><h3> Required Interpersonal Skills</h3><br/><ul> <br/> <li>  Strong communication skills with the ability to interact effectively across teams </li> <br/> <li>  Proven ability to collaborate with design, verification, IT and infrastructure teams </li> <br/> <li>  Experience working in multi-cultural global environments and coordinating with globally distributed teams </li> <br/></ul><br/><br/><h3> Nice-to-Have</h3><br/><ul> <br/> <li>  Exposure to AI-assisted verification workflows / LLM-based tools and AI Agents development. </li> <br/> <li>  Experience with cloud-based or distributed regression environments </li> <br/> <li>  Interest in automating repetitive support workflows across DV flows using scripting or AI-based approaches </li> <br/> <li>  Experience as CAD Application Engineer in EDA vendor company </li> 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