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Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human  </span>  <span>   ingenuity  </span>  <span>   and a shared passion to create something extraordinary. When you join AMD,  </span>  <span>   you'll  </span>  <span>   discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond.  </span>  <span>  </span> </span> <strong>  <span>   <span>    Together, we advance your career.   </span>  </span> </strong> <span> </span></p><br/><strong class=\"jdheading\"></strong><br/><br/><p> <strong>  PMTS SILICON DESIGN ENGINEER </strong></p><p></p><p> <strong>  THE PERSON: </strong> <br/> You have a passion for modern, complex processor architecture, digital design as well as verification/design quality. You are a team player who has excellent communication skills, strong analytical &amp; problem-solving skills and are willing to learn and ready to take on problems. A global mindset and ability to work in a multi – site environment are keys to being successful in this role.</p><p></p><p> <strong>  KEY RESPONSIBILITIES: </strong> <br/> RTL design of high performance x86-core ISA features, clock/reset/power features of processor, IP Integration, sub-system level design <br/> Architect and design of power management features, cache, coherency. <br/> Design optimization for implementing power efficient IP, implementing the RTL using low power techniques <br/> Responsible for the inter IP integration issues resolution <br/> Own the Clock-Domain crossing, Linting aspects of the overall design of the IP and the subsystem. <br/> Work closely with DFT, Physical Design and SOC teams to incorporate the interdisciplinary feedback into the design <br/> Architecting, micro-architecting and documentation of the design features <br/> Lead design team from all aspects of the RTL deliverables. <br/> Mentor the junior members of the RTL team to meet the team goals <br/> Represents AMD to the outside technical community, partners and vendors <br/> Your commitment to innovating as a team demonstrated through excellent communication, knowledge of proper documentation techniques, and independently driving tasks to completion.</p><p> <br/> <strong>  PREFERRED EXPERIENCE: </strong> <br/> 15+ years of experience in Digital IP/ASIC design and Verilog RTL development <br/> Experience in full IP design cycle, requirements definition, architecture and microarchitecture specification. <br/> Should be well versed with RTL design verification, design quality checks, synthesis, timing closure and post silicon validation. <br/> Expert on Verilog RTL design and has experience of multiscale digital IP/ASIC projects. <br/> Should possess expertise in front-end EDA tools sign-off and its flows. <br/> Familiarity with low power design and low power flow is an added plus. <br/> Ability to program with scripting languages such as Python or Perl is a plus; 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