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The ideal candidate should have hands-on experience in\n <strong>\n  Assertion-Based Verification (ABV)\n </strong>\n , property checking, and formal verification methodologies for complex digital designs.\n</p>\n<p>\n Key Responsibilities\n</p>\n<ul>\n <li>\n  Perform\n  <strong>\n   Formal Verification\n  </strong>\n  for IP/Sub-system/SoC level designs using Cadence JasperGold.\n </li>\n <li>\n  Develop and debug\n  <strong>\n   SystemVerilog Assertions (SVA)\n  </strong>\n  and formal properties.\n </li>\n <li>\n  Execute:\n </li>\n <li>\n  Property Verification\n </li>\n <li>\n  Connectivity Checks\n </li>\n <li>\n  X-Propagation Analysis\n </li>\n <li>\n  Deadlock Detection\n </li>\n <li>\n  Equivalence Checking\n </li>\n <li>\n  Understand RTL architecture and create formal verification plans.\n </li>\n <li>\n  Collaborate with RTL, DV, and Architecture teams for verification closure.\n </li>\n <li>\n  Analyze counterexamples, debug failures, and identify root causes.\n </li>\n <li>\n  Improve design quality through assertion coverage and formal methodologies.\n </li>\n <li>\n  Support verification sign-off activities and documentation.\n </li>\n</ul>\n<p>\n Required Skills\n</p>\n<ul>\n <li>\n  4+ years of experience in\n  <strong>\n   ASIC/SoC Verification\n  </strong>\n  with strong focus on\n  <strong>\n   Formal Verification\n  </strong>\n  .\n </li>\n <li>\n  Hands-on expertise in:\n </li>\n <li>\n  Cadence JasperGold\n </li>\n <li>\n  SystemVerilog\n </li>\n <li>\n  SVA (SystemVerilog Assertions)\n </li>\n <li>\n  Verilog/VHDL\n </li>\n <li>\n  Strong understanding of:\n </li>\n <li>\n  Digital Design Fundamentals\n </li>\n <li>\n  RTL Design Concepts\n </li>\n <li>\n  Assertion-Based Verification (ABV)\n </li>\n <li>\n  Formal Verification Flow\n </li>\n <li>\n  Experience with industry-standard protocols:\n </li>\n <li>\n  AXI\n </li>\n <li>\n  AHB\n </li>\n <li>\n  APB\n </li>\n <li>\n  PCIe\n </li>\n <li>\n  USB\n </li>\n <li>\n  Scripting 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